{\rtf1\ansi\ansicpg1252\cocoartf949\cocoasubrtf430 {\fonttbl\f0\fswiss\fcharset0 Helvetica;} {\colortbl;\red255\green255\blue255;} \margl1440\margr1440\vieww12240\viewh15840\viewkind1 \pard\tx720\tx1440\tx2160\tx2880\tx3600\tx4320\tx5040\tx5760\tx6480\tx7200\tx7920\tx8640\ql\qnatural\pardirnatural \f0\fs24 \cf0 Mini seq fix\ \ \ Description: Clocking jumps stages when in high speed.\ Specifically, when one stage is providing CV to the clock (for non-equal timing), a stage set "fast" will produce clock pulses that make the sequencer jump past further stages or even latch-up in high speed mode.\ \ Problem: spurious clock signals affecting master clock\ \ Cure: add capacitance to final clock output (F1 or P1) to ground through .047- .1uf cap.\ \ }